1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to the testing of electronic circuits.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
As computer system technology has advanced, the operating speed of various bus bridging devices has increased dramatically. Bus speeds on computer system motherboards have increased correspondingly, thereby increasing the efficiency at which computer systems can process transactions.
One drawback to the use of high-speed bus bridging devices is reduced testability. Bus bridging devices are typically implemented as integrated circuits mounted within a package. These integrated circuit packages successfully pass production tests before they may actually be used in a computer system. However, many production test systems are incapable of sending or receiving test data at the same speeds at which the bus bridging devices normally operate. This drawback makes it difficult to verify that the external interfaces of the bus bridging device will operate properly when placed in a computer system, as some may pass test at lower speeds but fail to properly function at higher speeds. Conversely, test systems that can function at higher speeds are typically much more expensive than testers configured for testing lower speed devices.
Additional problems may be created by the nature of the device tested. In devices that have a clock forwarding architecture, they problem of accumulated phase error may make it difficult, if not impossible to test the device on a clock synchronous tester. Devices having a clock forwarding architecture may encounter phase slippage during their operation, and this phase slippage may cause the clock and data signals to drift by one or more bit time. Since the clock and data signals are transmitted at the same time, the operation of the device may not be affected by the phase slippage. However, when testing the device on a synchronous tester, phase slippage may cause false failures. Thus, the false failures resulting from phase slippage, along with operational speeds that exceed the capabilities of most testers result in devices that may be untestable.